1. Field of the Invention
The present invention relates to a timer input control circuit and its counter control circuit, particularly to a circuit allowing read-on-the-fly and write-on-the-fly operations of counter values even if the timer input signal does not synchronize with the system clock.
2. Description of the Prior Art
FIG. 7 shows the configuration of a timer input control circuit according to the prior art, in which numeral 2 is a timer count enabling/inhibiting signal, 3 is a timer input signal, and 9 is a counter input signal.
FIG. 8 shows the timer count operation waveform of the above timer input control circuit, in which numeral 1 is system clock, 2 is a timer count enabling/inhibiting signal, 3 is a timer input signal, 9 is a counter input signal, 21 is a counter operation waveform, and 22 is a spike-shaped counter input signal.
The following is the description of operations. First, the timer input signal is input and then supplied to the counter as the counter input signal only when the timer count enabling/inhibiting signal is effective. Therefore, when the timer count enabling/inhibiting signal is inhibited immediately after the timer input signal rises, the spike-shaped counter input signal is generated as shown by numeral 22 in FIG. 8.
For the conventional timer using a ripple counter, the above spike-shaped timer count signal is influenced only by the least significant bit of the timer counter when the count input signal does not synchronize with the system clock. However, a count value error has no problem for practical use. In this case, read-on-the-fly operation of timer count values cannot be executed because each bit change timing of the ripple counter differs.
Even if a read register is installed and a count source and read control signal are controlled from being transferred to the read register by an SR flip-flop, the upper limit of the operating frequency lowers if the counter has a lot of bits. Also, because the spike-shaped signal is given to the count source, there are problems that the above flip-flop operation is unstable and so on. Therefore, the purpose of the conventional timer is restricted.
To realize the read-on-the-fly operation, a synchronous counter to simultaneously update all bits at the time of counting is used. However, if the count input control circuit shown in FIG. 7 is used to switch the enabling/inhibiting operation of the counter, count values may greatly vary because the above spike-shaped pulse is input to the clock at each stage of the synchronous counter. Therefore, normal counting cannot be made if the counter input signal does not synchronize with the operation of the input control circuit. That is, it is necessary to sample the counter input signal by the system clock for driving the input control circuit and synchronize it. Therefore, it is impossible to use the frequency of the counter input signal higher than that of the system clock. Thus, for the conventional timer having the read-on-the-fly function, it is impossible to count or stop the timer input signal with the frequency higher than that of the system clock when enabling or inhibiting the counter operation.